1. Field of Invention
The present invention relates to a method of manufacturing an integrated circuit device isolation structure. More particularly, the present invention relates to a method of manufacturing shallow trench isolation (STI) structure.
2. Description of Related Art
Device isolation regions are generally used for preventing the flow of mobile carriers from one device to its neighboring devices through the substrate. Conventionally, device isolation regions are formed between neighboring field effect transistors (FET) of densely packed semiconductor circuits such as dynamic random access memories (DRAMs). These device isolation regions are capable of reducing charge leakage from the field effect transistors. In general, device isolation regions take the form of an extended layer of thick oxide above a semiconductor substrate formed by a local oxidation of silicon (LOCOS) method. As fabrication using the LOCOS techniques gradually matures, highly reliable device isolation structure can be obtained at low cost. However, the LOCOS method of forming isolation structure has a number of problems including the possible generation of large internal stress and the bird's beak encroachment at the periphery of the field oxide layer. In particular, as devices are miniaturized, the bird's beak encroachment region will become so large that using LOCOS field oxide to isolate devices is infeasible.
Another commonly used method of isolating devices is the shallow trench isolation (STI). In general, a STI structure is formed by depositing a silicon nitride layer over a semiconductor substrate, then patterning the silicon nitride layer to form a hard mask. Next, the substrate is etched to form steep-sided trenches between neighboring devices. Finally, oxide material is deposited into the trenches to form device isolation structure that has roughly the same height as the original substrate surface.
FIGS. 1 through 7 are cross-sectional views showing the progression of manufacturing steps in producing shallow trench isolation structure according to a conventional method.
First, as shown in FIG. 1, an oxide layer 22 is formed over a silicon substrate 10. The oxide layer 22 is a pad oxide layer whose function is to protect the substrate surface, and hence will ultimately be removed before the gate oxide layer is formed. Thereafter, a chemical vapor deposition (CVD) process is used to form a silicon nitride layer 24 over the oxide layer 22. Next, photoresist is deposited over the silicon nitride layer 24, and then photolithographic process is used to develop a patterned photoresist layer 28. Subsequently, the patterned photoresist layer 28 is used as a mask to etch away a portion of the silicon nitride layer 24, the pad oxide layer 22 and the silicon substrate 10. Hence, a trench 30 is formed in the substrate 10. Thereafter, the photoresist layer 28 is removed.
Next, as shown in FIG. 2, a thermal oxidation method is used to form a linear oxide layer 31 lining the surface of the trench 30. Thereafter, a silicon oxide layer 32 is formed by depositing silicon oxide material into the trench 30 and overflowing to cover the silicon nitride layer 24 as well. The silicon oxide layer 32 is formed by an atmospheric pressure chemical vapor deposition method (APCVD) using tetra-ethyl-ortho-silicate (TEOS) as gaseous reactant. The TEOS oxide layer 32 needs to be densified, and therefore must be heated to about 1000.degree. C. for about 10 to 30 minutes. After the densification operation, the TEOS oxide will contract a little.
Next, as shown in FIG. 3, using the silicon nitride layer 24 as an etching stop, a chemical-mechanical polishing (CMP) method is used to remove the TEOS oxide layer lying above the silicon nitride layer 24. Ultimately, oxide plugs 34 remain inside the trenches 30. Because the oxide plug 34 is softer than the surrounding silicon nitride material, a tiny portion of oxide material on the upper surface of the oxide plug 34 is removed forming minor recesses.
Next, as shown in FIG. 4, the silicon nitride layer 24 is removed exposing a portion of the oxide plug 34 above the pad oxide layer 22. The silicon nitride layer 24 can be removed using hot phosphoric acid solution, for example.
Next, as shown in FIG. 5, the pad oxide layer 22 is removed by immersing in hydrofluoric acid. Since the TEOS oxide plug 34 has a considerably higher etching rate than the pad oxide layer 22, a thicker layer of oxide plug material will be removed by the time the pad oxide layer 22 is completely removed. Ultimately, the TEOS oxide plugs 34 will be roughly at the same height level as the substrate surface.
Next, as shown in FIG. 6, a sacrificial oxide layer 36 is formed over the substrate 10 acting as a protective layer. Then, according to the needs of a particular device, one or more ion implants are carried out to adjust the channel threshold voltage.
Next, as shown in FIG. 7, hydrofluoric acid solution is again used to remove the sacrificial oxide layer 36. In the etching operation, over-etching of the oxide plug 34 often occurs. Consequently, recesses are often formed on the upper surface of the oxide plugs 34. These recesses are at a level below the substrate surface 10 and are labeled 38 and 39 in FIG. 7.
In the presence of these recesses 38, subthreshold kink effect will be intensified resulting in abnormal subthreshold current, and hence will turn on the channel of a transistor erroneously.
In light of the foregoing, there is a need to provide an improved method of manufacturing shallow trench isolation structure.